A prior microprocessor based computer system typically includes memories in order to store instructions and/or data for processing. The memories typically include volatile memories. The content stored in a prior volatile memory is typically lost if the power supply to the prior computer system is disrupted. One type of prior volatile memories is a dynamic random access memory ("DRAM"). A prior DRAM typically includes a plurality of DRAM cells, each storing one bit of data. The information is typically stored in a prior DRAM cell in the form of electrical charge. When the charge stored in a DRAM cell is less than a certain voltage level (e.g., 0.5 volts), it indicates a logical zero value, for example. When the charge stored in that particular DRAM cell is greater than a certain voltage level (e.g., 1.8 volts), it indicates a logical one value, for example.
A prior DRAM cell typically loses its electrical charge over a period of time, which may result in the logical content of the cell charging. Therefore, it is necessary to refresh the prior DRAM cell. The refresh of a prior DRAM cell typically involves the steps of reading out the content stored in that cell and then writing it back to that cell. During the writing back step of the refresh operation, the cell will be charged above the voltage level representing the content stored.
The refresh operation is typically periodically performed to the prior DRAM. A refresh timer is typically provided in the prior computer system to periodically trigger the refresh operation. One prior arrangement of using a refresh timer to periodically activate the refresh operation is illustrated in FIG. 1.
Referring to FIG. 1, a prior computer system 10 is shown which includes a CPU 11 coupled to a host bus 12 via line 11a. A DRAM 14 is also coupled to host bus 12 via line 14a and to a system bus 18 via fine 14b. DRAM 14 is controlled by a DRAM controller 13. System bus 18 is also connected to a plurality of system devices 20a through 20n. System devices 20a-20n may typically include at least one volatile memory. The bus activities of system bus 18 is controlled by a system bus controller 15. System bus controller 15 is also coupled to DRAM controller 13.
A refresh timer 16 is provided in computer system 10. Refresh timer 16 is coupled to system bus controller 15 via line 17a and to DRAM controller 13 via line 17b. Refresh timer 16 is set to generate a refresh signal to DRAM controller 13 via line 17b and to system bus controller 15 via line 17a at every 15 microseconds. DRAM controller 13 then performs a memory refresh operation to DRAM 14 and system bus controller 15 performs the refresh operation to the system devices that require the refresh. The refresh operation typically takes one microsecond to finish. During the refresh operation, CPU 11 and system bus 18 are both held non-operational. This arrangement is typically referred to as "coupled refresh."
One disadvantage of this prior arrangement is that CPU 11 is held off and no bus activity can occur on system bus 18 during the memory refresh operation. CPU 11 cannot access any of the system devices 20a through 20n that does not require the memory refresh operation. In other words, computer system 10 is not operative for 1 microsecond at every 15 microseconds.
A prior improvement of the above-described prior arrangement is illustrated in FIG. 2. In FIG. 2, computer system 30 includes a DRAM refresh timer 36 coupled to a DRAM controller 33, and a system refresh timer 37 coupled to a system bus controller 35. DRAM refresh timer 36 generates a memory refresh signal to DRAM controller 33 at a predetermined time interval. The predetermined time interval is typically 15 microseconds. Upon receiving the memory refresh signal, DRAM controller 33 then performs the memory refresh operation to DRAM 34. System refresh timer 37 generates a system memory refresh signal to system bus controller 35 at another predetermined time interval which can also typically be 15 microseconds. System refresh timer 37 generates its system memory refresh signal independent of the generation of the memory refresh signal from DRAM refresh timer 36. Upon receiving the system memory refresh signal, system bus controller 35 starts to perform the memory refresh operation to system devices 40a-40n, regardless of whether there is a system volatile memory among system devices 40a-40n. In addition, system bus controller 35 refreshes system devices 40a-40n independent of the occurrence of the DRAM refresh operation to DRAM 34. In other words, the system memory refresh operation is asynchronously performed with the DRAM refresh operation. In this case, CPU 31 may not necessarily be held off in refresh state during the memory refresh of DRAM 34 and may access system devices 40a-40n. Moreover, CPU 31 may access DRAM 34 when system bus controller 35 is performing the memory refresh operation to system devices 40a-40n.
One disadvantage of this prior arrangement is that the CPU access to the system bus is restricted when the system bus controller is performing the system memory refresh operation. Whenever the system bus controller is performing the refresh operation, the CPU cannot access any of the system devices that does not require the memory refresh operation via the system bus. In this case, the CPU resource is still wasted. Another disadvantage is that the memory refresh operation is performed regardless whether there is a volatile memory among system devices 40a-40n.